Completing the MOV16 opcode

Over the last few days I have completed the soldered version of the MOV16 opcode. The task of the MOV16 opcode is to move the content of a 16-bit wide register into another one. The following VHDL code shows the simulated version of the opcode.

As you can see from the implementation, it generates the necessary control signals to:

  • Transfer the data from the source register onto the address bus (Select Control Signals)
  • Transfer the data from the address bus into the destination register (Load Control Signals)

In addition the MOV16 opcode has to decode from 3 bits the source and destination register. Here I’m using 2 simple 3-to-8 decoders, which are also simulated with the following VHDL code:

The following picture shows the 4 soldered modules: the two 3-to-8 decoders, and the 2 modules that generate the Select and Load Control signals:

The individual soldered modules

In addition I have on a 5th PCB board the logic which tests for the MOV16 opcode (01DDDSSS), which drives the whole Instruction Decoder. The following picture shows the 5 mounted PCB boards:

The completed Instruction Decoder for the MOV16 opcode

The green wires are the timing signals from the state machine (the CPU can be in 8 different states), and the blue wires are the current 8-bit wide instruction to be executed (which gets decoded and executed by the module if it is the MOV16 opcode). The black wires are the power lines (VCC, GND).

With that module in place I’m now already able to prepare a 16-bit wide memory address in a specific register as the following assembly code shows:

In that case the 16-bit wide M register holds the memory address, which is then used for the LOAD and STORE opcode to read and write from/to the SRAM memory. That’s now the next step that I want to complete over the next few days. Stay tuned 🙂

Thanks for your time,


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