Welcome to my 8-bit RISC based CPU project. The goal of the project is to implement a 8-bit RISC based CPU only with primitive 74LS TTL gates (AND, OR, XOR, NOT). Use the following interactive graphic (or the menu above) to explore and understand the various parts of my custom developed CPU.
SRAM Memory
Das ist ein Test von Klaus Aschenbrenner...
Instruction Decoder
ALU
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