Performs a OR operation between both 8-bit wide input values. The following listing shows the VDHL description of the OR operation.
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entity OR8Bit is Port ( InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value ); end OR8Bit; architecture Behavioral of OR8Bit is begin Output(0) <= InputA(0) or InputB(0); Output(1) <= InputA(1) or InputB(1); Output(2) <= InputA(2) or InputB(2); Output(3) <= InputA(3) or InputB(3); Output(4) <= InputA(4) or InputB(4); Output(5) <= InputA(5) or InputB(5); Output(6) <= InputA(6) or InputB(6); Output(7) <= InputA(7) or InputB(7); end Behavioral; |